1. Field of the Invention
The present invention relates to transceivers for concurrently transmitting and receiving signals through unshielded twisted pairs, and particularly to a transceiver employing a high efficiency driver and providing echo cancellation.
2. Description of Related Art
The IEEE 802.3ab (“Ethernet”) standard defines a digital media interface commonly used for transmitting data between computers linked through a network. The standard includes a “1000BASE-T” protocol enabling transceivers to communicate with one another through pulse amplitude modulation (PAM) signals conveyed on a set of four category 5 (CAT5) unshielded twisted-pair (UTP) conductors. A transceiver operating in accordance with the 1000BASE-T protocol can transmit and receive one 8-bit word every 8 nsec, thereby providing an effective communication rate of one Gigabit per second in both directions.
Since each bit combination of a data word may be treated as a symbol, for example representing a number or letter, an 8-bit word can be any of 256 different symbols. A 1000BASE-T transceiver maps the 256 symbols into combinations of voltage levels of the set of four PAM signals, and it can change the PAM signal voltage levels every 8 ns.
As a differential 1000BASE-T signal passes from a transmitter to a receiver via a UTP conductor it is distorted in various ways. When the signal has relatively few transitions during a relatively long period, it acts as a low frequency signal. Magnetic coupling modules that link the UTP cables to the transceivers act like high pass filters which attenuate low frequency signal components, thereby causing a type of distortion known as “baseline wander”. “Insertion loss” is signal distortion caused by attenuation through the impedance of the UTP cable conveying the 1000BASE-T signals between transceivers. Since 1000BASE-T transceiver can transmit and receive signals concurrently over the same twisted pair, its outgoing signal can cause “echo” distortion in the incoming signal. Since the four UTP are bundled into the same cable and are unshielded, an outgoing signal departing on any one of the UTPs will cause some “near end crosstalk ” (NEXT) distortion in the signals departing on the other UTPs and an incoming 1000BASE-T signal arriving on any one UTP will cause some “far end crosstalk” (FEXT) distortion in the incoming signals arriving on the other three UTPs. Since the four UTPs may have slightly different number of twists per unit length, the actual lengths of the four UTPs within the same cable may differ, and the four UTPs may provide differing signal path delays. Therefore the four signals passing over the four UTPs can have a timing mismatch when they arrive at a receiver. 1000BASE-T transceivers include circuits for compensating incoming 1000BASE-T signals for all of these types of distortion.
1000BASE-T Transceiver
FIG. 1 illustrates a prior art 1000BASE-T transceiver 10 in block diagram form. Transceiver 10 includes a transmit physical coding sublayer (PCS) 12 for scrambling and encoding an incoming sequence of 8-bit words (DATA_IN) to produce four separate sequences of 3-bit data words Txa–Txd, each of which represents an integer value of the set {−2, −1, 0, +1 or +2} referencing one of five PMA-5 symbols. Each data sequence Txa–Txd is supplied as input to a separate one of a set of four transceivers 14A–14D, each of which transmits an outgoing 1000BASE-T signal on a separate one of four UTPs 16. The Txa–Txd sequence input to each transceiver 14A–14D controls the level of its outgoing 1000BASE-T signal. Each transceiver 14A–14D also detects the data sequence Rxa–Rxd conveyed by a separate one of the incoming 1000BASE-T signals arriving on UTPs 16 and supplies it as input to PCS 12. PCS 12 decodes and de-scrambles the Rxa–Rxd sequences to generate a data sequence (DATA_OUT) conveyed by the four incoming 1000BASE-T signals.
Each transceiver 14A–14D includes a pulse shaper 16 for converting its input Txa–Txd sequence into a data sequence indicating the shape of the outgoing 1000BASE-T signal to be produced. A digital-to-analog converter (DAC) 18 converts that sequence into an analog signal, and a low pass filter 20 filters the DAC output signal to produce a differential signal V1. A driver within a hybrid 24 amplifies the V1 signal to produce the outgoing 1000BASE-T signal transmitted on UTP 16.
Hybrid 24 receives the incoming 1000BASE-T signal arriving on UTP 16 and provides it as an input signal V2 to an amplifier 26 having gain and offset controlled by signals G1 and OFF1. A low pass filter 28 and an analog-to-digital converter (ADC) 30 filter and digitize the incoming signal V2 to produce a sequence of data elements D1. An automatic gain control (AGC) circuit 32 monitors D1 and controls the gain G1 of receiver to compensate for insertion loss and to make sure that the peak-to-peak amplitude of the ADC's analog input signal remains close to the its full input range. A FIFO buffer 34 delays the D1 sequence to produce a sequence D2 that is synchronized to local clocks. An adaptive feedforward equalizer (FFE) 36 compensates the D2 sequence for distortions introduced by UTP 16 to produce a sequence D3.
Echo Cancellation
Although hybrid 24 cancels much of the echo of the outgoing 1000BASE-T signal in the V2 signal supplied to amplifier 26, some echo distortion caused by the outgoing 1000BASE-T signal remains in the V2 signal and the D3 sequence. Since the outgoing 1000BASE-T signals departing other three UTPs 16 also induce near end crosstalk (NEXT) distortion in incoming 1000BASE-T signal that distortion is reflected in the V2 signal and the D3 sequence. An echo/NEXT canceller circuit 40 monitors the Txa–Txd sequence received by all four transceivers 14 and supplies an offset data sequence OFF2 to a summer 38 representing the magnitude of echo and NEXT distortion that the four outgoing signals produce in the incoming 1000BASE-T signal. Summer 38 subtracts the OFF2 sequence generated by echo/NEXT canceller 40 from the data sequence D3 produced by FFE 36 to produce a data sequence D4. Digital signal processing circuits 42 process the D4 sequence to detect and forward the Rxa sequence input to PCS 12, to produce clock signals for controlling FIFO buffer 34 and ADC 30, and to provide the OFF1 control input to amplifier 26.
The amplitudes of the incoming and outgoing 1000BASE-T signals are additive at the hybrid's input/output terminals, and if hybrid 24 did not cancel most of the echo from the V2 signal, then in the worst case the peak-to-peak amplitude of the V2 signal would be about twice as large. Echo/NEXT canceling circuit 40 could be adapted to cancel all of the outgoing 1000BASE-T signal echo from the D3 data sequence derived from V2, but in order to achieve the same resolution over twice the range, ADC 30 would have to be increased in width by an extra bit. Adding a bit to ADC 30 doubles the number of components within ADC 30 and substantially increases the transceiver's power consumption. Hence it is preferable to provide a hybrid 24 that cancels as much of the echo of the outgoing 1000BASE-T signal as possible from the V2 signal supplied to amplifier 26.
Hybrid
FIG. 2 illustrates a typical hybrid 24 in more detail. A class A driver 48 amplifies the V1 signal to produce a pair of currents I1 and I2 supplied to nodes 54A and 54B at opposite ends of a primary winding of a transformer 50 having a center tap tied to a voltage source VDD. FIG. 3 is a timing diagram illustrating an example 5-level V1 waveform and FIGS. 4 and 5 show the behavior of the output currents I1 and I2 driver 48 produces in response to the V1 signal. Note that output current I1 and I2 of the class A driver 48 are symmetric about a non-zero current level and that they both continuously vary with the magnitude or polarity of V1.
Referring again to FIG. 2, a pair of load resistors RXA and RXB and a capacitor CX couple nodes 54A and 54B to ground. UTP 16 links the secondary winding of transformer 50 to a remote transceiver 52 modeled by its input/output resistance RL. The V2 signal supplied to amplifier 26 of FIG. 1 is produced by an amplifier 56 having inverting and non-inverting inputs respectively coupled to nodes 55A and 55B. A resistor R2A links the output and inverting input of amplifier 56 and a resistor R2B couples its noninverting input to ground. A pair of resistors R1 and R2 link nodes 54A and 54B to nodes 55A and 55B. The V2 signal represents an amplified difference between the voltages VYA and VYB at the amplifier inputs.
The magnitudes of the voltages VXA and VXB developed at nodes 54A and 54B, and therefore voltages VYA and VYB at the amplifier inputs result partly from the load seen by the output currents I1 and I2 of driver 48 and partly from the load seen by the currents induced in the transformer's primary winding by the incoming 1000BASE-T signal from remote transceiver 52. Hybrid 24 includes echo cancellation circuits for canceling the effects of driver output currents I1 and I2 on the voltages VYA and VYB at the inputs of amplifier 56 so that its output signal V2 reflects primarily the magnitude of the incoming 1000BASE-T signal.
The echo cancellation circuit for current I1 includes a resistor network R3A and R4A and a current source I3. Current source I3 and a current source within driver 48 producing current I1 form a current mirror such that current source I3 produces a relatively small output current that is proportional to current I1. Resistors R3A and R4A are coupled in series between VDD and the inverting input of driver 56A, and the current output of source I3 is delivered to the node between resistors R3A and R4A. Resistors R1A–R4A are suitably made relatively large so that they do not present a significant load to current I1.
The voltage drop across load resistor RXA is proportional to the current it conducts. One portion of that current is provided by source I1 and tends to pull down on VXA, thereby reducing the current input to node 55A. Another portion or the current through RXA is provided by transformer 50 in response to the incoming 1000BASE-T signal. Thus the voltage VXA at node 54A and the voltage VYA at node 55A at the inverting input of amplifier 56 are both influenced by current I1 and by the incoming 1000BASE-T signal. However with current I3 being proportional to current I1 and with resistors R3A and R4A being appropriately scaled, the voltage VKA developed by source I3 will supply a current I5 into node 55A that matches the reduction in current into node 55A resulting from the resistive load RXA on current I1. Thus while the portion of the current I1 passing through load resistor RXA influences VYA, the echo compensation circuit formed by resistors R3A, R4A and current source I3 cancels that influence. Hybrid 24 includes another echo cancellation circuit including a resistors R3B and R4B and a current source I4 mirroring current 12 for supplying a current I6 into node N4 canceling the effects of I2 resistive loading on the voltage VYB at the non-inverting input of amplifier 56.
The two echo cancellation circuits therefore cancel the portion of the echo of the outgoing 1000BASE-T signal due to the load on currents I1 and I2 provided by resistors RXA and RXB and load RL on the other side of transformer 50. However the contributions of currents I1 and I2 to voltages VXA and VXB are influenced not only by the resistive loads on I1 and I2, but also by the reactive load associated with the leakage inductance of transformer 50 appearing in parallel with RXA and RXB. Since prior art hybrid 24 of FIG. 2 only cancels the effects on VXA and VXB due to the resistive loads of RXA and RXB on I1 and I2 and does not cancel the effects on VXA and VXB due to their reactive loads, V2 will include echo distortion arising from the reactive loads on I1 and I2.
Class A Driver
Another undesirable feature of hybrid 24 is that its class A driver 48 dissipates substantial amounts of power. Driver 48 is a class A amplifier because, as illustrated in FIGS. 4 and 5, both its output currents I1 and I2 continuously track variations in V1. Since currents I1 and I2 are always on, they continuously dissipate power in resistors RXA and RXB and in their internal transistors in proportion to the sum of the root mean square (RMS) magnitudes of the two current signals.
Class B and AB Drivers
Unlike 1000BASE-T systems, 10BASE-T systems transmit signals in one direction on each UTP, and some 10BASE-TX transmitters employ class B or AB amplifiers as drivers. FIG. 6 illustrates a simple class AB amplifier 62 including a pair of current sources IA and IB supplying currents to output nodes 50 and 52 and a pair of resistors RXA and RXB linking nodes 50 and 52 to a voltage source. FIG. 7 illustrates a typical differential OUTPUT signal waveform driver 62 would generate in response to its INPUT signal. FIGS. 8 and 9 depict the IA and IB waveforms that produce the OUTPUT waveform of FIG. 7. When the INPUT signal is driven positive, current source IA turns fully on and current source IB turns nearly off, and the OUTPUT signal is driven to a +1 volt level. When the INPUT signal is 0 volts, both sources IA and IB turn nearly off and the OUTPUT signal falls to 0 volts. When the INPUT signal is driven negative, source IA nearly turns off, source IB turns fully on, and the OUTPUT signal is driven to a −1 volt level. As seen in FIGS. 8 and 9, class AB amplifier currents IA and IB are asymmetric and that only one of the currents tracks variations in V1 at a time; the other current is nearly off, providing only a small quiescent output current to limit cross-over distortion in the OUTPUT signal. A class B amplifier behaves in a similar manner except that current sources IA and IB fully turn off.
Class B or AB drivers have less power consumption than class A drivers. Since IA and IB are fully on and track changes in the V1 signal only part of the time, they have relatively low RMS values and cause substantially less power dissipation than the currents produced by class A drivers.
When transceiver systems transmit over unidirectional UTPs there is no need for echo cancellation. However class B and AB drivers have not been used in 1000BASE-T systems because they cause a type of echo that has been problematic. In the 1000BASE-T hybrid illustrated in FIG. 2, The VYA and VYB signals are symmetric about a stable common mode voltage. If we were to replace the class A driver 48 with a class B or AB driver, then VYA and VYB would no longer be symmetric and would have a varying common mode voltage. When V1 is negative, I1 is off (class B) or nearly off (class AB) and I2 is fully on, and current I2 would tend to pull VXA above VDD through the inductance of transformer 50, thereby pulling up on the voltage VYA at the inverting input of amplifier 56. Conversely when V1 is positive and I2 is off or nearly off and I1 is fully on, I1 would pull up on VXB, thereby causing an increase in voltage VYX at the non-inverting input of amplifier 56. The variations in VYA and VYB track variations in V1 and produce substantial echo distortion in the output V2 of amplifier 56.
What is needed is 1000BASE-T transceiver employing a more power efficient class B or AB driver which not only properly cancels echo in the output voltage due to the driver's resistive load, but also cancels echo due to the driver's reactive load and due to the asymmetric nature of the class B or AB driver's output signals.